Abstract

Positioned as a highly promising post-CMOS computing technology, superconductor electronics (SCE) offer the potential for unparalleled performance and energy efficiency gains compared to end-of-roadmap CMOS circuits. However, achieving very large-scale integration poses numerous challenges. These challenges span from the modeling and analysis of superconducting devices and logic gates to the intricate design of complex SCE circuits and systems. Addressing power and clock distribution issues, minimizing adverse effects of flux trappings, and mitigating stray electromagnetic fields in sensitive SCE circuitry are key challenges that need attention. Verification and testing of SCE circuits also remain open problems. Moreover, scaling the minimum feature sizes of SCE circuits, currently set at 150nm, presents critical scaling and physical design challenges that must be overcome. This review aims to delve …

Metadata

publication

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024

year

2024

publication date

2024/3/25

authors

Sasan Razmkhah, Robert S Aviles, Mingye Li, Sandeep Gupta, Peter A Beerel, Massoud Pedram

link

https://ieeexplore.ieee.org/abstract/document/10546830/

source

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)

pages

1-6

publisher

IEEE