Abstract

This paper proposes an efficient asynchronous hardwired matrix-vector multiplier for the rwo-dimensional discrete cosine transform and inverse discrete cosine transform (DCT/IDCT). The design achieves low power and high performance by taking advantage of the typically large fraction of zero and small-valued data in DCT and IDCT applications. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit-partitioned adders using simplified, static-logic-based speculative completion sensing. The results extracted by both bit-level analysis and HSPICE simulations indicate significant improvements compared to traditional designs.

Metadata

publication

Proceedings of the 2000 international symposium on Low power electronics and …, 2000

year

2000

publication date

2000/8/1

authors

Kyeounsoo Kim, Peter A Beerel, Youpyo Hong

link

https://dl.acm.org/doi/abs/10.1145/344166.344621

resource_link

https://dl.acm.org/doi/pdf/10.1145/344166.344621

book

Proceedings of the 2000 international symposium on Low power electronics and design

pages

256-261