Abstract

A method for fabricating low defective non-planar bipolar heterostructure transistors includes a steps of providing a substrate that is coated with a first dielectric layer when the substrate is not composed of a dielectric material. A layer of a first semiconductor material is formed by template liquid phase (TLP) crystal growth wherein a second dielectric layer is disposed over the first semiconductor material. A trench is patterned into the second dielectric layer. An intermediate heterostructure is formed by epitaxially growing second semiconductor material in the trench to form a fin structure therein. Various power transistor structures can be formed from the intermediate heterostructure.

Metadata

publication

US Patent App. 18/579,330, 2024

year

2024

publication date

2024/9/12

authors

AP Jacob, RR Kapadia

link

https://patents.google.com/patent/US20240304703A1/en

inventors

Ajey Poovannummoottil Jacob, Rehan Rashid Kapadia

patent_office

US

application_number

18579330