Abstract

Security, speed, and energy efficiency are critical for computing applications in general and for edge applications in particular. Digital In-Memory Computing (IMC) in SRAM cells has widely been studied to accelerate inference tasks to maximize both throughput and energy efficiency for intelligent computing at the edge. XOR operations have been of particular interest due to their wide applicability in numerous applications that include binary neural networks and encryption. Based on monte-carlo simulation on commercial Globalfoundries 22nm node, we are proposing a novel 9T SRAM cell enabling multiple rows of data (entire array) to be XORed in a massively parallel single cycle fashion, compared to XOR of two rows in prior IMC works. The new cell also supports array-level data-toggling, using the least number of transistors compared to previous works, within the SRAM cell efficiently to circumvent imprinting …

Metadata

publication

Proceedings of the Great Lakes Symposium on VLSI 2024, 277-281, 2024

year

2024

publication date

2024/6/12

authors

Zihan Yin, Annewsha Datta, Shwetha Vijayakumar, Ajey Jacob, Akhilesh Jaiswal

link

https://dl.acm.org/doi/abs/10.1145/3649476.3658789

resource_link

https://dl.acm.org/doi/pdf/10.1145/3649476.3658789

book

Proceedings of the Great Lakes Symposium on VLSI 2024

pages

277-281