Abstract

The present disclosure relates to a structure including a differential memory array circuit which is configured to perform a binary convolution of two input word operands by accumulating a summation of currents through a plurality of bits which are each arranged between a wordline and a sourceline in a horizontal direction and bitlines in a vertical direction.

Metadata

publication

US Patent App. 16/366,187, 2020

year

2020

publication date

2020/10/1

authors

A Agrawal, AP Jacob

link

https://patents.google.com/patent/US20200311533A1/en

resource_link

https://patentimages.storage.googleapis.com/8b/f4/53/15a0c0a507c6f7/US20200311533A1.pdf

inventors

Amogh Agrawal, Ajey Poovannummoottil Jacob

patent_office

US

application_number

16366187