Abstract

(57) ABSTRACT A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed.
Embodiments include forming plural fins on a silicon sub strate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Metadata

publication

US Patent 10,756,213, 2020

year

2020

publication date

2020/8/25

authors

MH Chi, A Jacob, A Paul

link

https://patents.google.com/patent/US10756213B2/en

resource_link

https://patentimages.storage.googleapis.com/54/40/dc/ed4c311abde908/US10756213.pdf

inventors

Min-Hwa Chi, Ajey Jacob, Abhijeet Paul

patent_office

US

patent_number

10756213

application_number

16433626