Abstract

The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory com putations.(58)

Date

November 5, 2019

Authors

AR Jaiswal, AP Jacob

Inventors

Akhilesh R Jaiswal, Ajey Poovannummoottil Jacob

Patent_office

US

Patent_number

10468084

Application_number

15944032