Publications
Logic-in-memory computations for non-volatile resistive random access memory (RAM) array
Abstract
The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory com putations.(58)
Metadata
- publication
- US Patent 10,468,084, 2019
- year
- 2019
- publication date
- 2019/11/5
- authors
- AR Jaiswal, AP Jacob
- link
- https://patents.google.com/patent/US10468084B2/en
- resource_link
- https://patentimages.storage.googleapis.com/6f/57/ab/f1a8a8c9e7dfcb/US10468084.pdf
- inventors
- Akhilesh R Jaiswal, Ajey Poovannummoottil Jacob
- patent_office
- US
- patent_number
- 10468084
- application_number
- 15944032