Abstract

A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include form ing first trenches in a Si, Ge, III-V, or Si, Ge-x substrate; forming a conformal SiN, SiO CN, layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or Si, Ge-substrate; removing exposed portions of the Si, Ge, III-V, or Si, Ge. substrate, forming second trenches; forming III-V, III-VM, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VM,, or Si nanowires and intervening first trenches; removing the SiO, layer, forming third trenches; and removing the second m

Metadata

publication

US Patent 10,319,642, 2019

year

2019

publication date

2019/6/11

authors

SK Patil, AP Jacob

link

https://patents.google.com/patent/US10319642B2/en

resource_link

https://patentimages.storage.googleapis.com/8e/fb/4e/b07692800f6399/US10319642.pdf

inventors

Suraj Kumar Patil, Ajey P Jacob

patent_office

US

patent_number

10319642

application_number

15667305