Abstract

One illustrative method disclosed herein includes forming a gate structure above a portion of a fin and performing a first epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above the fin in the source and drain regions of a FinFET device. In this example, the method also includes performing a heating process so as to form a source/drain graphene contact from the silicon-carbide (SIC) semiconductor material in both the source and drain regions of the FinFET device and forming first and second source/drain contact structures that are conductively coupled to the source/drain graphene contact in the source region and the drain region, respectively, of the FinFET device.

Metadata

publication

US Patent 9,972,537, 2018

year

2018

publication date

2018/5/15

authors

AP Jacob

link

https://patents.google.com/patent/US9972537B2/en

resource_link

https://patentimages.storage.googleapis.com/a0/ea/02/2cb3dfbd4be42f/US9972537.pdf

inventors

Ajey Poovannummoottil Jacob

patent_office

US

patent_number

9972537

application_number

15052098