Abstract

Modern computing systems require enhanced performance; however, the conventional memories such as Static Random Access Memory (SRAM) are inadequate to support this demand. This is mainly due to the fact that SRAM density cannot be increased commensurately with Complementary Metal-Oxide–Semiconductor (CMOS) transistor scaling. For example, typically the six-transistor (6T) SRAM, which has long been the workhorse of high-performance caches, requires a cell size of where F is the feature size [1]. On the other hand, Spin-Transfer Torque based Magnetoresistive Random-Access Memory (STT-MRAM) have emerged as universal memory technology due to its non-volatility, endurance, low operating voltages and ultrafast switching [2]. Further, they occupy much less area with 1T design comparable to DRAM with cell size of [1]. Thus, STT-MRAM is most suited for on-chip cache applications with highest possible …

Metadata

publication

2018 IEEE International Magnetics Conference (INTERMAG), 1-1, 2018

year

2018

publication date

2018/4/23

authors

H Dixit, S Agarwal, D Datta, A Jacob, D Shum, F Benistant

link

https://ieeexplore.ieee.org/abstract/document/8508685/

conference

2018 IEEE International Magnetics Conference (INTERMAG)

pages

1-1

publisher

IEEE