Abstract

ABSTRACT A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow there through while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.

Metadata

publication

US Patent 9,754,903, 2017

year

2017

publication date

2017/9/5

authors

SK Patil, MH Chi, AP Jacob

link

https://patents.google.com/patent/US9754903B2/en

resource_link

https://patentimages.storage.googleapis.com/09/26/bb/8177350b0b030a/US9754903.pdf

inventors

Suraj K Patil, Min-Hwa Chi, Ajey Poovannummoottil Jacob

patent_office

US

patent_number

9754903

application_number

14926880