Abstract

Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of frontend of line (FEOL) processing. Towards the end of the FEOL process ing, the dummy Spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Metadata

publication

US Patent 9,368,591, 2016

year

2016

publication date

2016/6/14

authors

SJ Bentley, AP Jacob, CY Chen, T Yamashita

link

https://patents.google.com/patent/US9368591/en

resource_link

https://patentimages.storage.googleapis.com/e8/ed/7b/7cc6e54730b5d8/US9368591.pdf

inventors

Steven J Bentley, Ajey Poovannummoottil Jacob, Chia-Yu Chen, Tenko Yamashita

patent_office

US

patent_number

9368591

application_number

14334950