Abstract

A method of forming a multi-valued logic transistor with a Small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon Sub strate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top por tion of the fin having a thickness equal to a thickness of each Si-based layer, and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Metadata

publication

US Patent 9,362,277, 2016

year

2016

publication date

2016/6/7

authors

MH Chi, A Jacob, A Paul

link

https://patents.google.com/patent/US9362277B2/en

resource_link

https://patentimages.storage.googleapis.com/2c/4d/35/5d03c16548efbb/US9362277.pdf

inventors

Min-Hwa Chi, Ajey Jacob, Abhijeet Paul

patent_office

US

patent_number

9362277

application_number

14175827