Publications
Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices
Abstract
One illustrative method disclosed herein includes, among other things, forming a first episemiconductor material in a Source/drain region of a transistor device, the first episemi conductor material having a first lateral width at an upper Surface thereof, forming a second episemiconductor material on the first episemiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second episemiconductor material has a second lateral width at an upper Surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper Surface of the second episemi conductor material.
Metadata
- publication
- US Patent 9,318,552, 2016
- year
- 2016
- publication date
- 2016/4/19
- authors
- R Xie, WJ Taylor Jr, AP Jacob
- link
- https://patents.google.com/patent/US9318552B2/en
- resource_link
- https://patentimages.storage.googleapis.com/c2/92/29/650c02e2ac7362/US9318552.pdf
- inventors
- Ruilong Xie, William J Taylor Jr, Ajey Poovannummoottil Jacob
- patent_office
- US
- patent_number
- 9318552
- application_number
- 14283404