Abstract

One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of episilicon-ger manium (SiGe) is equal to or greater than a target concen tration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, form ing a gate structure around at least a portion of the SiGe region.

Metadata

publication

US Patent 9,245,980, 2016

year

2016

publication date

2016/1/26

authors

MK Akarvardar, JA Fronheiser, AP Jacob

link

https://patents.google.com/patent/US9245980B2/en

resource_link

https://patentimages.storage.googleapis.com/12/dc/c8/9dc7035291eaae/US9245980.pdf

inventors

Murat Kerem Akarvardar, Jody A Fronheiser, Ajey Poovannummoottil Jacob

patent_office

US

patent_number

9245980

application_number

14242472