Abstract

One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper Sur face of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the Substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semi conductor material.

Metadata

publication

US Patent 9,224,605, 2015

year

2015

publication date

2015/12/29

authors

Y Qi, AP Jacob, S Liang

link

https://patents.google.com/patent/US9224605B2/en

resource_link

https://patentimages.storage.googleapis.com/03/47/3f/5abced7853e0a6/US9224605.pdf

inventors

Yi Qi, Ajey Poovannummoottil Jacob, Shurong Liang

patent_office

US

patent_number

9224605

application_number

14267154