Abstract

Approaches for isolating source and drain regions in an integrated circuit (IC) device (eg, a fin field effect transistor (FinFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an undoped epitaxial (epi) layer between the embedded S/D and the gate structure. The device may further include an epitaxial (epi) bottom region of the embedded S/D, wherein the epi bottom region is counter doped to a polarity of the embedded S/D, and a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions is doped and the epi bottom region is undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal …

Date

May 21, 2015

Authors

AP Jacob, MK Akarvardar

Inventors

Ajey Poovannummoottil Jacob, Murat K Akarvardar

Patent_office

US

Application_number

14086199