Abstract

One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a Substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a pla narization process on the layer of insulating material to expose the patterned hard, performing a second etching pro cess to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material Such that an upper Surface of the insulating material is below an upper Surface of the second portion of the fin.

Metadata

publication

US Patent 8,580,642, 2013

year

2013

publication date

2013/11/12

authors

WP Maszara, AP Jacob, NV LiCausi, JA Fronheiser, K Akarvardar

link

https://patents.google.com/patent/US8580642B1/en

resource_link

https://patentimages.storage.googleapis.com/8b/a3/62/159f79c972ad0b/US8580642.pdf

inventors

Witold P Maszara, Ajey P Jacob, Nicholas V LiCausi, Jody A Fronheiser, Kerem Akarvardar

patent_office

US

patent_number

8580642

application_number

13476645