Abstract

Logic locking has become a promising approach to provide hardware security in the face of a possibly insecure fabrication supply chain. While many techniques have focused on locking combinational logic (CL), an alternative latch-locking approach in which the sequential elements are locked has also gained significant attention. Latch (LAT) locking duplicates a subset of the flip-flops (FF) of a design, retimes these FFs and replaces them with latches, and adds two types of decoy latches to obfuscate the netlist. It then adds control circuitry (CC) such that all latches must be correctly keyed for the circuit to function correctly. This paper presents a two-phase attack on latch-locked circuits that uses a novel combination of deep learning, Boolean analysis, and integer linear programming (ILP). The attack requires access to the reverse-engineered netlist but, unlike SAT attacks, is oracle-less, not needing access to the …

Metadata

publication

2023 24th International Symposium on Quality Electronic Design (ISQED), 1-8, 2023

year

2023

publication date

2023/4/5

authors

Dake Chen, Xuan Zhou, Yinghua Hu, Yuke Zhang, Kaixin Yang, Andrew Rittenbach, Pierluigi Nuzzo, Peter A Beerel

link

https://ieeexplore.ieee.org/abstract/document/10129346/

resource_link

https://arxiv.org/pdf/2305.00107

conference

2023 24th International Symposium on Quality Electronic Design (ISQED)

pages

1-8

publisher

IEEE